ROS 2 Nodes Get Zero-Copy CUDA Transport via rosidl::Buffer

NVIDIA's Isaac ROS 5.0 stack now uses the CUDA buffer backend for rosidl::Buffer, a ROS 2 Lyrical abstraction that lets nodes exchange GPU-resident payloads through zero-copy transport when runtime conditions allow. The backend, contributed by NVIDIA to ROS Lyrical, implements rosidl::Buffer storage with CUDA Virtual Memory Management. When publisher and subscriber meet requirements, payloads move between co-located nodes without serialization or host copies. Otherwise, ROS 2 falls back to the CPU path compatible with any existing node. The optimized path requires the same host, CUDA device, Linux user, and a supported RMW implementation such as rmw_fastrtps_cpp or rmw_zenoh_cpp.

The migration workflow

NVIDIA published a tutorial using the Depth Anything 3 TensorRT ROS 2 node as a migration example. The node's callback converts incoming ROS images to OpenCV views, runs monocular metric-depth inference with TensorRT, converts the result back to a ROS image, and publishes it as a floating-point depth image. The original CPU-backed ROS boundary surrounded a GPU-native algorithm, creating unnecessary host transfers, allocations, and serialization work.

An AI coding agent uses the migrate-node-to-rosidl-buffer skill to audit the node. The skill directs the agent to record the starting revision and target environment, confirm message field type compatibility, trace each message field from receipt to publication including CUDA calls and stream ownership, run a read-only copy-boundary audit, make a per-field migration plan, implement the smallest interface-preserving patch, and verify semantics and memory-copy behavior independently.

Key node changes

The migration adds cuda_buffer and cuda_buffer_backend packages as dependencies while keeping the sensor_msgs/msg/Image message definition unchanged. The subscriber accepts CUDA-backed buffers through subscription options, with CPU remaining an acceptable fallback by default, so the node-level callback does not need separate CPU and CUDA implementations.

The TensorRT inference writes results directly into CUDA buffer-backed message storage. The node allocates the output message's data field with cuda_buffer_backend::allocate_buffer, extracts input and output handles with from_input_buffer and from_output_buffer, and runs inference on the TensorRT stream. The inner scope releases the write handle after work is enqueued, recording a CUDA event before publication to ensure operation ordering. The publish call remains the same, with CUDA memory sharing handled automatically by the middleware and backends.

Optional CPU work stays separate. Point-cloud construction and debug visualization are local CPU consumers in the original node, and when enabled they may still require host access to the data. The skill keeps that non-CUDA route intact, preserving the node's contract while allowing the output Image.data field to carry CUDA-backed storage.

Verification uses NVIDIA Nsight Systems to confirm the absence of payload-sized host-device transfers at the ROS boundary, and checks that msg->data.get_backend_type() reports "cuda" when both endpoints meet requirements. The resulting workload can be deployed on NVIDIA Jetson AGX Thor. NVIDIA provides the migrate-node-to-rosidl-buffer agent skill for download, along with Isaac ROS 5.0 and documentation for the ROS 2 Lyrical rosidl::Buffer capability.