AMD MI455X vs MI355X: Serving Ratios and Component Benchmarks

AMD published a technical breakdown of the inference numbers it shared at Advancing AI 2026, comparing the new Instinct MI455X (Helios) accelerator with the current-generation MI355X. The post covers an end-to-end serving benchmark on DeepSeek-V4-Flash and a set of component microbenchmarks for compute, memory bandwidth, and networking. All results are reported as MI455X-to-MI355X ratios, with each microbenchmark run five times and the median reported. The MI455X ran on a pre-release Helios bringup platform, so the numbers reflect a specific point in software enablement and may shift with later ROCm and framework releases.

The serving benchmark used DeepSeek-V4-Flash, an open-source Mixture-of-Experts model with 284B total parameters and 13B activated per token. Expert weights are stored in FP4 precision, most other parameters in FP8, and the model supports context lengths up to one million tokens. Both GPUs served the model through AMD's ATOM inference stack on a single GPU. AMD swept concurrency at two fixed sequence-length settings: 1K/1K (1,024-token input, 1,024-token output) and 1K/8K (1,024-token input, 8,192-token output). The headline ratio is computed at fixed interactivity thresholds, meaning AMD found the highest total throughput each GPU can deliver while still meeting a given output-tokens-per-second-per-user target.

Serving Ratios at Fixed Interactivity

At the 1K/1K setting, the throughput ratio climbed from 2.47x at a 20 tokens/s/user threshold to 33.98x at a 90 tokens/s/user threshold. Intermediate points include 3.70x at 30, 7.44x at 40, 12.66x at 50, 14.79x at 60, 17.06x at 70, and 30.46x at 80. At the 1K/8K setting, the ratio reached 2.79x at 20, 4.39x at 30, 5.30x at 40, 15.38x at 50, 17.74x at 60, 32.20x at 70, and 33.52x at 80. AMD notes the ratio depends on the threshold because the two curves have different shapes: at relaxed targets both GPUs are near their throughput ceilings, while at demanding targets the MI355X curve drops off and the MI455X still serves a large concurrent batch.

Component Microbenchmarks

AMD isolated three building blocks behind the serving gains. For compute, it timed an MXFP4 GEMM from AITER, AMD's AI operator library for ROCm, at M=4096, N=4096, K=262144 with MXFP4 inputs and BF16 compute and output. This is an apples-to-apples comparison, and a single MI455X reached up to 3.3x higher MXFP4 performance than a single MI355X, reported as 20.0 PFLOPS against 6.0 PFLOPS. AMD cautions that the trigonometric initialization pattern used a very slow period, making inputs near-constant and yielding a peak-delivered figure, and that it reports a conservative 20.0 PFLOPS rather than the higher figure the microbenchmark reached.

For memory bandwidth, AMD used a bandwidth-bound MLA decode kernel from AITER, tuned to push sustained HBM bandwidth on each GPU. This is a peak-to-peak comparison, since the kernels are each tuned for their target GPU. MI455X came out ahead by up to 3.8x higher bandwidth than MI355X on this benchmark, with a 1.9x compute lead; the bandwidth ratio being larger indicates the kernel is genuinely bandwidth-bound, which is the regime decode lives in. AMD also ran networking benchmarks, which by definition involve more than one endpoint. The component results explain why MI455X holds a good experience across more of the concurrency range, with the steepest serving gains at the high-interactivity end where the MI355X curve drops below successive concurrency steps.